resistor self heating

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diff --git a/module-design.typ b/module-design.typ
index ca44492..fddd468 100644
--- a/module-design.typ
+++ b/module-design.typ
@@ -2274,6 +2274,98 @@ $qtyrange(1, 5, "year")$ without ratiometric cancellation or derating.
 / Periodic reference recalibration: Recalibrate baseline offsets against the
   system $plus.minus qty(10.0000, "V")$ reference standard.
 
+===== Resistor self-heating <resistor-self-heating>
+
+====== Physical mechanism <resistor-self-heating-physical-mechanism>
+
+Electrical power dissipation in a resistor raises the internal element
+temperature above the surrounding ambient amient environment and PCB substrate:
+
+$ Delta T_"self" = P . theta_(J A) $
+
+Where $theta_(J A)$ is the thermal resistance from junction to ambient
+$unit("celsius per watt")$.
+
+This localized temperature rise causes an immediate, signal-dependent
+resistance change via the tempco, and accelerates long-term Arrhenius aging.
+
+====== Mathematical model <resistor-self-heating-mathematical-model>
+
+For a resistor carrying current $I$ under voltage drop $V$:
+
+$
+               P & = I^2 R = V^2 / R \
+  Delta T_"self" & = I^2 R dot theta_(J A) \
+   (Delta R)/R_0 & = alpha_1 dot V^2 / R_0 dot theta_(J A)
+$
+
+Because the resistance change is proportional to $V^2$, self-heating creates a
+_signal-dependent_ non-linear error that introduces second-harmonic distortion
+($V^3 / R_0$ current term) and dynamic thermal memory.
+
+====== Typical magnitude <resistor-self-heating-typical-magnitude>
+
+For a $qty(10, "kilo ohm")$ through-hole precision resistor
+($theta_(J A) approx qty(100, "celsius per watt")$) withn a
+$qty(25, "ppm per celsius")$ tempco, passing $qty(1, "mA")$ ($qty(10, "V")$
+signal):
+
+#let p = calc.pow(0.001, 2) * 10000
+#assert-aeq(p, apply-prefix(10, "milli"))
+#let t_self = apply-prefix(10, "milli") * 100
+#assert.eq(t_self, 1)
+#let delta_r_r = 25 * 1
+#assert.eq(delta_r_r, 25)
+$
+               P & = 0.001^2 times 10000 = qty(10, "mW") \
+  Delta T_"self" & = qty(10, "mW") times qty(100, "celsius per watt") = qty(1, "celsius") \
+     (Delta R)/R & = 25 times 1 = qty(25, "ppm")
+$
+
+A $qty(25, "ppm")$ resistance shift produces a $qty(500, "mV")$ systematic
+error on a $qty(20, "V")$ full-scale signal, consuming $qty(250, "percent")$ of
+the entire $qty(10, "ppm")$ Metrologic systematic error budget.
+
+For dynamic signals, this creates a time-varying error that lags the signal
+envelope with a characteristic thermal time constant
+$tau_"th" = C_"th" dot theta_(J A)$ (typically
+$qtyrange(0.1, 10, "s")$).
+
+====== Where it enters <resistor-self-heating-where-it-enters>
+
+/ High-voltage-swing summing resistors: Resistors experiencing large voltage
+  variations ($plus.minus qty(10, "V")$) at op-amp input nodes.
+/ Feedback networks: Errors in feedback resistors are directly multiplied by the
+  closed-loop noise gain.
+/ Current-to-voltage converters ($I/V$ stages): High signal currents drive
+  non-linear self-heating in sense resistors, generating harmonic distortion.
+
+====== Scaling law <resistor-self-heating-scaling-law>
+
+- Self-heating power dissipation scales quadratically with applied voltage
+  ($V^2$) or current ($I^2$).
+- Temperature rise scales linearly with package thermal resistance
+  $theta_(J A)$, which decreases as physical component footprint and thermal
+  copper area increase.
+- Dynamic thermal memory error tracks the low-pass filtered power envelope
+  $P(t) * e^(-t / tau_"th")$.
+- In differential configurations, if both resistors experience identical power
+  dissipation ($P_1 = P_2$) and share identical thermal impedance, ratio shift
+  cancels to first order ($Delta (R_1 / R_2) arrow 0$).
+
+====== Compensation strategy <resistor-self-heating-compensation-strategy>
+
+/ Power derating: Oversize physical package ratings (e.g., using $qty(0.5, "W")$
+  through-hole) to operate resistors at $lt qty(10, "percent")$ rated capacity,
+  lowering $theta_(J A)$.
+/ Ultra-low tempco elements: Bulk metal foil resistors with
+  $alpha_1 lt.eq qty(0.2, "ppm per celsius")$ reduce self-heating error by
+  $125 times$ (to $lt qty(0.2, "ppm")$).
+/ Symmetrical differential layout: Design gain stages so that paired resistors
+  dissipate equal power, maintaining ratio invariance.
+/ Current reduction: Increase circuit impedance levels where feasible, balancing
+  self-heating reduction against Johnson noise constraints.
+
 == Error compensation strategies <error-compensation-strategies>
 
 == Advanced compensation topologies <advanced-compensation-topologies>