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@@ -2186,6 +2186,94 @@ $lt qty(0.2, "ppm per celsius")$ ($qty(200, "ppb per celsius")$).
 
 ===== Resistor aging and load life <resistor-aging-and-load-life>
 
+====== Physical mechanism <resistor-aging-and-load-life-physical-mechanism>
+
+Resistors undergo long-term, irreversible baseline resistance changes over
+operational lifetime due to four primary physical processes:
+
+/ Oxidation: Moisture and ambient oxygen slowly react with the resistive film or
+  foil element, altering effective conductive cross-sectional area.
+/ Mechanical stress relaxation: Internal lattice strains induced during wire
+  drawing, foil rolling, or laser trimming gradually relax over time.
+/ Electromigration: High DC current densities cause momentum transfer from
+  charge carriers to metal lattice ions, resulting in physical mass transport.
+/ Moisture absorption: Protective epoxy or silicone encapsulants absorb ambient
+  moisture, altering dielectric properties and creating parasitic leakage
+  channels.
+
+These degradation mechanisms are thermally accelerated following Arrhenius
+dynamics and exacerbated by power dissipation and ambient humidity cycling.
+
+====== Mathematical model <resistor-aging-and-load-life-mathematical-model>
+
+Unstressed shelf-life aging is modeled logarithmically over decades of
+operational time:
+
+$ (Delta R)/R = A dot ln(t/t_0) $
+
+Where:
+- $A$ is the material aging coefficient ($unit("ppm per decade")$ of time).
+- $t_0$ is the initial stabilization epoch (typically $qty(1000, "hour")$
+  post-fabrication).
+
+Alternatively, for load-life aging under electrical power dissipation $P$:
+
+$ (Delta R)/R = B dot (P / P_0)^n dot sqrt(t/t_0) $
+
+Where $P_0$ is nominal rated power, $0.5 lt.eq n lt.eq 1.0$ is the empirical
+power exponent, and $B$ is the load-life stability factor.
+
+====== Typical magnitude <resistor-aging-and-load-life-typical-magnitude>
+
+#include "tables/resistor-aging-and-load-life-typical-magnitude.typ"
+
+For Metrologic tier ($qty(10, "ppm")$ total systemic budget), unpassivated
+precision thin-film resistors ($qty(500, "ppm")$ per $qty(1000, "hour")$ load
+life) consume the 30-day budget ($qty(10, "ppm")$) within the first
+$qty(20, "hour")$ of continuous operation.
+
+Even ultra-stable bulk metal foil resistors ($qty(10, "ppm")$ per
+$qty(1000, "hour")$ under full load) would consume the budget within
+$qtyrange(1, 5, "year")$ without ratiometric cancellation or derating.
+
+====== Where it enters <resistor-aging-and-load-life-where-it-enters>
+
+/ Absolute reference scaling dividers: Resistors setting the
+  $+10.0000 upright("V")$ and $-10.0000 upright("V")$ system reference
+  standards.
+/ Integrator time constants: Resistor drift in $tau = R C$ directly alters state
+  trajectory integration rates in time-domain compute cores.
+/ Gain-determining feedback ratios: Unmatched discrete feedback resistors in
+  summing amplifiers and attenuators.
+
+====== Scaling law <resistor-aging-and-load-life-scaling-law>
+
+- Long-term baseline aging scales sub-linearly with time, following a
+  square-root ($sqrt(t)$) or logarithmic ($ln(t)$) relaxation trajectory.
+- Power-induced aging scales with power density $(P / P_0)^n$ and accelerates
+  exponentially with operating junction temperature via Arrhenius thermal
+  acceleration ($exp(-E_a / (k_B T))$).
+- In monolithic matched networks, aging mismatch between adjacent elements on
+  the same ceramic substrate scales at less than $qty(5, "percent")$ of absolute
+  single-element aging
+  ($Delta R_("aging","ratio") < 0.05 dot Delta R_("aging","abs")$), because
+  both elements share identical thermal, electrical, and metallurgical stress
+  histories.
+
+====== Compensation strategy <resistor-aging-and-load-life-compensation-strategy>
+
+/ Power derating: Operate precision resistors at $lt qty(10, "percent")$ of
+  their nominal rated power ($P lt.eq qty(10, "mW")$) to keep internal junction
+  self-heating below $qty(1, "celsius")$.
+/ Pre-conditioning burn-in: Subject resistor networks to powered thermal
+  pre-aging ($qty(168, "hour")$ at $qty(125, "celsius")$) prior to initial
+  calibration to pass the steep initial logarithmic drift region.
+/ Monolithic ratiometric design: Utilize integrated resistor networks where
+  aging tracking ($Delta R_("aging","ratio")$) governs circuit performance
+  rather than absolute drift.
+/ Periodic reference recalibration: Recalibrate baseline offsets against the
+  system $plus.minus qty(10.0000, "V")$ reference standard.
+
 == Error compensation strategies <error-compensation-strategies>
 
 == Advanced compensation topologies <advanced-compensation-topologies>