same.git - SAME Analog Modular Ecosystem

Age	Commit message (Collapse)	Author	Files	Lines
8 hours	add ratio-stability-principle chart	Denis Chevalier	1	-3/+8

8 hours	add resistor-tempco (start drift sources)	Denis Chevalier	2	-4/+149

17 hours	Add default vscode configuration	Denis Chevalier	2	-0/+38

17 hours	typo in README.md, add git hook for new typ files SPDX header	Denis Chevalier	3	-2/+46

17 hours	Add a nvim local config to automatically insert relevant license information ↵	Denis Chevalier	1	-0/+32
	on new typ files
18 hours	Add header to all typ files	Denis Chevalier	94	-0/+1038

18 hours	Add LLM policy	Denis Chevalier	2	-0/+77

18 hours	Add CODE-OF-CONDUCT.md	Denis Chevalier	1	-0/+81

18 hours	Add CONTRIBUTING.md	Denis Chevalier	1	-0/+158

18 hours	Add README.md	Denis Chevalier	1	-0/+99

19 hours	update licensing to add GPLv3 for code	Denis Chevalier	5	-6/+1469

20 hours	cleaning up and properly typesetting emdashes	Denis Chevalier	5	-9/+16

20 hours	reduce charts samples to 1000 to reduce compile load and ram usage	Denis Chevalier	4	-15/+15

20 hours	rename assert_aeq.typ and apply_prefix.typ s/_/-/	Denis Chevalier	3	-2/+2

20 hours	extract figures in separate files	Denis Chevalier	89	-4174/+4339

23 hours	replace chassis module loading svg	Denis Chevalier	2	-908/+483

24 hours	replace grid svg with cetz	Denis Chevalier	2	-1180/+338

25 hours	replace db-25 connector cutout svg with cetz	Denis Chevalier	2	-614/+293

25 hours	replace ventilation svg with cetz	Denis Chevalier	2	-1259/+361

25 hours	replace front panel geometry with cetz diagram	Denis Chevalier	2	-651/+247

25 hours	switch u-channel diagram from svg to cetz	Denis Chevalier	3	-1384/+193

26 hours	complete l-channel diagram	Denis Chevalier	1	-7/+422

26 hours	replace cassette external dimensions svg with cetz drawing	Denis Chevalier	2	-631/+218

27 hours	generate figure 1 (db-25 backplane connector) using cetz	Denis Chevalier	2	-1056/+124

27 hours	formatting, graphs, potentiometer wiper noise and wear, crosstalk	Denis Chevalier	2	-73/+738

33 hours	Add assertion to check the maths early on, and fix typos	Denis Chevalier	3	-33/+113

35 hours	load add-unit via lib/unify.typ in preamble	Denis Chevalier	2	-2/+2

35 hours	push unify.lib into its own lib subdirectory	Denis Chevalier	5	-4/+4

35 hours	set per and delimiter parameters globally (curry unify methods)	Denis Chevalier	5	-136/+123

43 hours	inductor losses and parasitic effects	Denis Chevalier	1	-0/+119

44 hours	capacitor dielectric absorption noise, triboelectric and piezoelectric ↵	Denis Chevalier	1	-83/+282
	effects, and pcb leakage currents
2 days	more shertz and continue error enumeration	Denis Chevalier	2	-26/+248

2 days	add shertz (square hertz) custom unit	Denis Chevalier	2	-20/+28

2 days	uniformize unit formating with fractions, and range formating with to	Denis Chevalier	4	-73/+88

2 days	continue errors enumeration	Denis Chevalier	2	-6/+227

3 days	update where it enters for resistor thermal noise	Denis Chevalier	1	-3/+13

3 days	fix custom units and num for times 10^(-n)$ constructions	Denis Chevalier	2	-57/+57

3 days	start error budgeting section and use widely uVrms	Denis Chevalier	2	-17/+291

3 days	use @ syntax for refs	Denis Chevalier	4	-24/+24

3 days	fix typos	Denis Chevalier	1	-5/+6

3 days	write 4.1 and 4.2	Denis Chevalier	3	-51/+922

3 days	add module design introduction	Denis Chevalier	2	-1/+99

3 days	finish mechanical specifications	Denis Chevalier	3	-0/+1288

3 days	Improve global project (typos, enforce 80 columns whenever possible, ↵	Denis Chevalier	12	-66/+7465
	diagrams) and finish 3.1
4 days	do not push pdf files	Denis Chevalier	2	-9587/+1

4 days	advance on cassette mechanical specifications	Denis Chevalier	2	-3729/+6232

4 days	Start writing specification	Denis Chevalier	5	-0/+8313